(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a grooved gate, metal oxide semiconductor field effect transistor, (MOSFET), device.
(2) Description of Prior Art
Grooved gate MOSFET devices have allowed the semiconductor industry to achieve the objectives of increased device density, and device performance. The ability to form a polysilicon, grooved gate structure, featuring deep sub-micron dimensions, obtained using the dimensions of the groove formed in the semiconductor substrate, in place of conventional polysilicon gate structures, defined via photolithographic and dry etching procedures, have allowed reductions in MOSFET area to be realized, thus resulting in increased device density. In addition the use of grooved gate technology has resulted in the suppression of short channel effects, encountered with conventional deep sub-micron, polysilicon gate, MOSFET devices. However the ability to form grooves with consistent depths, in all regions of the semiconductor substrate, has limited the use of grooved gate MOSFET devices.
This invention will teach a procedure in which the depth of the groove in the semiconductor substrate, is accurately controlled using a groove pattern, formed in an insulator layer, then using a reactive ion etching, (RIE), procedure, to form the grooves in the semiconductor substrate, with the RE procedure featuring a specific etch rate ratio between the insulator layer, and the silicon of the semiconductor substrate. The thickness of the masking insulator layer, and the RIE etching ambient, with a specific etch rate ratio, are chosen to result in complete removal of this masking insulator layer, at a point in which the desired depth of the groove in silicon is achieved. Additional etching, after removal of the masking insulator layer, will remove all exposed silicon at the same rate thus maintaining the desired groove depth, achieved at the point of consumption of the masking insulator layer. Prior art, such as Leung, in U.S. Pat. No. 4,729,815, as well as Nguyen et al, in U.S. Pat. No. 5,821,169, describe methods of forming patterns in silicon using RIE procedures, but these prior arts do not show the novelty of this invention using a masking insulator pattern, with a specific thickness designed to allow a desired depth for grooves in silicon, to be achieved, when using a RIE procedure, with a specific etch rate ratio, or etch selectivity, between the masking insulator layer, and the silicon semiconductor substrate.